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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:15:59 03/16/2012 
-- Design Name: 
-- Module Name:    IOclock - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.definitions.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IOclock is
    Port ( clk_i : in  STD_LOGIC;
           clk_o : out  STD_LOGIC;
			  
			  instr_ack_i : in  STD_LOGIC;
           instr_word_i : in  STD_LOGIC_VECTOR (17 downto 0);
           data_ack_i : in  STD_LOGIC;
           data_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           port_ack_i : in  STD_LOGIC;
           port_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
			  cu_status : in state_type;
			  cu_mem_op : in STD_LOGIC;
			  ena_mem_port_data : in STD_LOGIC;
			  mem_rw : in STD_LOGIC;
			  datapath_word_o : in STD_LOGIC_VECTOR (7 downto 0);
			  datapath_addr_o : in STD_LOGIC_VECTOR (7 downto 0);
			  
			  pc : in  STD_LOGIC_VECTOR (9 downto 0);
			  		  
			  instr_reg : out STD_LOGIC_VECTOR (17 downto 0);
			  data_reg : out STD_LOGIC_VECTOR (7 downto 0);
           instr_cyc_o : out  STD_LOGIC;
           instr_stb_o : out  STD_LOGIC;
           instr_addr_o : out  STD_LOGIC_VECTOR (9 downto 0);
           data_cyc_o : out  STD_LOGIC;
           data_stb_o : out  STD_LOGIC;
			  data_we_o : out STD_LOGIC; 
           data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           data_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
           port_cyc_o : out  STD_LOGIC;
           port_stb_o : out  STD_LOGIC;
           port_we_o : out  STD_LOGIC;
           port_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           port_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
			  instr_ack_to_cu : out STD_LOGIC;
			  data_ack_to_cu : out STD_LOGIC;
			  port_ack_to_cu : out STD_LOGIC);			  
end IOclock;

architecture Behavioral of IOclock is

component IOInterface
		port(instr_ack_i : in  STD_LOGIC;
           instr_word_i : in  STD_LOGIC_VECTOR (17 downto 0);
           data_ack_i : in  STD_LOGIC;
           data_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           port_ack_i : in  STD_LOGIC;
           port_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
			  cu_status : in state_type;
			  cu_mem_op : in STD_LOGIC;
			  ena_mem_port_data : in STD_LOGIC;
			  mem_rw : in STD_LOGIC;
			  datapath_word_o : in STD_LOGIC_VECTOR (7 downto 0);
			  datapath_addr_o : in STD_LOGIC_VECTOR (7 downto 0);
			  
			  pc: in  STD_LOGIC_VECTOR (9 downto 0);
			  		  
			  instr_reg : out STD_LOGIC_VECTOR (17 downto 0);
			  data_reg : out STD_LOGIC_VECTOR (7 downto 0);
           instr_cyc_o : out  STD_LOGIC;
           instr_stb_o : out  STD_LOGIC;
           instr_addr_o : out  STD_LOGIC_VECTOR (9 downto 0);
           data_cyc_o : out  STD_LOGIC;
           data_stb_o : out  STD_LOGIC;
			  data_we_o : out STD_LOGIC; 
           data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           data_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
           port_cyc_o : out  STD_LOGIC;
           port_stb_o : out  STD_LOGIC;
           port_we_o : out  STD_LOGIC;
           port_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           port_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
			  instr_ack_to_cu : out STD_LOGIC;
			  data_ack_to_cu : out STD_LOGIC;
			  port_ack_to_cu : out STD_LOGIC);
end component;

begin
	io_interface: IOInterface Port map (
							  instr_ack_i => instr_ack_i,
							  instr_word_i => instr_word_i,
							  data_ack_i => data_ack_i,
							  data_word_i => data_word_i,
							  port_ack_i => port_ack_i,
							  port_word_i => port_word_i,
							  cu_status => cu_status,
							  cu_mem_op => cu_mem_op,
							  ena_mem_port_data => ena_mem_port_data,
							  mem_rw => mem_rw,
							  datapath_word_o => datapath_word_o,
							  datapath_addr_o => datapath_addr_o,
							  pc => pc,
							  instr_reg => instr_reg,
							  data_reg => data_reg,
							  instr_cyc_o => instr_cyc_o,
							  instr_stb_o => instr_stb_o,
							  instr_addr_o => instr_addr_o,
							  data_cyc_o => data_cyc_o,
							  data_stb_o => data_stb_o,
							  data_we_o => data_we_o,
							  data_addr_o => data_addr_o,
							  data_word_o => data_word_o,
							  port_cyc_o => port_cyc_o,
							  port_stb_o => port_stb_o,
							  port_we_o => port_we_o,
							  port_addr_o => port_addr_o,
							  port_word_o => port_word_o,
							  instr_ack_to_cu => instr_ack_to_cu,
							  data_ack_to_cu => data_ack_to_cu,
							  port_ack_to_cu => port_ack_to_cu);
	clk_o <= clk_i;

end Behavioral;
